Microchip Technology /ATSAMV70J19B /TWIHS0 /SR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TXCOMP)TXCOMP 0 (RXRDY)RXRDY 0 (TXRDY)TXRDY 0 (SVREAD)SVREAD 0 (SVACC)SVACC 0 (GACC)GACC 0 (OVRE)OVRE 0 (UNRE)UNRE 0 (NACK)NACK 0 (ARBLST)ARBLST 0 (SCLWS)SCLWS 0 (EOSACC)EOSACC 0 (MCACK)MCACK 0 (TOUT)TOUT 0 (PECERR)PECERR 0 (SMBDAM)SMBDAM 0 (SMBHHM)SMBHHM 0 (SCL)SCL 0 (SDA)SDA

Description

Status Register

Fields

TXCOMP

Transmission Completed (cleared by writing TWIHS_THR)

RXRDY

Receive Holding Register Ready (cleared by reading TWIHS_RHR)

TXRDY

Transmit Holding Register Ready (cleared by writing TWIHS_THR)

SVREAD

Slave Read

SVACC

Slave Access

GACC

General Call Access (cleared on read)

OVRE

Overrun Error (cleared on read)

UNRE

Underrun Error (cleared on read)

NACK

Not Acknowledged (cleared on read)

ARBLST

Arbitration Lost (cleared on read)

SCLWS

Clock Wait State

EOSACC

End Of Slave Access (cleared on read)

MCACK

Master Code Acknowledge (cleared on read)

TOUT

Timeout Error (cleared on read)

PECERR

PEC Error (cleared on read)

SMBDAM

SMBus Default Address Match (cleared on read)

SMBHHM

SMBus Host Header Address Match (cleared on read)

SCL

SCL Line Value

SDA

SDA Line Value

Links

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